Inside TSMC's CoPoS: a new era for AI chip packaging

Imagine a thin pane of glass quietly remaking the innards of the world’s most powerful chips. That image captures the promise behind CoPoS, the packaging approach industry watchers say TSMC is developing.

The quiet revolution under glass

Sources familiar with the matter report that CoPoS stands for Chip-on-Panel-on-Structure. The method uses glass as a temporary carrier during assembly, and then that same glass is folded into the final substrate as a three-layer stack. It sounds simple. The implications are not.

Mass production is reportedly slated to begin by the end of 2028. The first high-profile customer said to be on board is Nvidia, which plans to use CoPoS for its Feynman AI chipset. That fits: next-generation packaging is aimed squarely at high-bandwidth, high-performance compute workloads where every millimeter of interconnect and every watt of power counts.

Why does this matter? Because packaging dictates how chips talk to memory and accelerators. CoPoS aims to shorten those links, increase I/O density, and offer cleaner thermal pathways. In plain terms: lower cost per function and higher sustained performance for AI and HPC designs. That combination is a rare commodity in semiconductor manufacturing.

There are risks and caveats. Integrating a temporary carrier into the final substrate is a complex ballet of materials and processes. Yield, thermal reliability, and long-term supply-chain readiness will determine whether CoPoS is evolutionary or revolutionary.

If CoPoS delivers at scale, TSMC could lock in a decisive advantage and force rivals to respond with their own packaging breakthroughs.

So what comes next? Expect close scrutiny from chip designers and system integrators. Expect competitors to accelerate R&D and to pursue alternative routes to similar gains. And expect CoPoS to become a yardstick for how the industry measures next-generation packaging performance.

Not every new technique pays off. But when a process promises both cost reduction and measurable performance gains for AI hardware, the whole supply chain pays attention.