Why AMD's EPYC Venice Could Outsell Nvidia's Vera in 2027

Picture a data center floor where racks hum like an orchestra warming up. The soloist everyone expects to lead? Nvidia. But the composition is shifting, and a new melody from AMD could steal the show.

How Venice gains the upper hand

Morgan Stanley’s latest read on the silicon landscape paints a nuanced picture. Nvidia will remain TSMC’s single largest CoWoS customer in 2027, but AMD’s next-generation EPYC lineup, codenamed Venice, is forecast to sell more CPU units than Nvidia’s Vera.

Numbers matter here. The bank projects Nvidia’s Vera shipments at about 5.75 million units in 2027. Big. Ambitious. Impressive for a new server CPU. Still, AMD’s Venice is forecast to hit roughly 6.75 million units — roughly 17 percent higher than Vera and a nearly 5.4x jump from AMD’s estimated 1.25 million-unit volume in 2026.

Several technical and market forces converge to explain that gap. Venice is built on Zen 6 and will leverage TSMC’s 2-nanometer process node. Vera, by contrast, targets agent-focused AI workloads and uses a 3-nanometer node. Venice aims to straddle both AI and high-performance computing tasks, broadening its addressable market.

Packaging and capacity are part of the story too. TSMC’s wafer capacity is expected to reach 200000 wafers per month in 2027, and Nvidia will still drive most of the CoWoS packaging demand. Morgan Stanley estimates CoWoS-L usage for Nvidia’s AI GPUs could climb to about 910000 units, up roughly 40 percent year over year. Vera’s shipments are also forecast to double, and combined trends like these help explain why Nvidia’s datacenter revenue could jump more than 50 percent year over year.

Yet raw demand numbers don’t tell the whole tale. Venice’s design—optimized for both AI inference and HPC—paired with a denser process node, gives AMD a wider set of workloads to capture. That versatility can translate into higher unit volume, especially among cloud providers balancing mixed workloads.

Then there’s the wildcard: custom silicon. Major AI players are investing heavily in bespoke chips. OpenAI, Google, Amazon, and others are either negotiating or moving toward in-house accelerators. When hyperscalers design and build their own silicon, they change the dynamics of supplier-driven demand. The emergence of custom silicon tightens the supply gap, adds unpredictability, and puts pressure on traditional vendors like Nvidia and AMD to compete not only against each other but against their customers.

So what should industry watchers watch for? First, adoption patterns among cloud providers: who opts for Venice versus Vera, and where do custom chips get deployed? Second, yield and ramp timelines at TSMC for both the 2nm and 3nm nodes—process maturity can swing advantage faster than design improvements. Third, CoWoS packaging capacity and priority allocation: even if demand exists, packaging throughput and scheduling matter.

At a high level, the next few years will be less about a single winner and more about strategic positioning. AMD’s Venice looks poised to take a unit-volume lead thanks to architecture choices and process advantages, but Nvidia’s dominance in AI GPU packaging and its entrenched datacenter relationships keep it squarely in the fight. Meanwhile, the rise of custom silicon adds a new opponent to the ring—one that could redraw market share maps in unexpected ways.

Expect volatility. Expect surprises. And expect server racks to keep humming, because demand for compute shows no sign of slowing down.